This invention relates to integrated circuits and, more particularly, to an improved comparator circuit with a novel bias arrangement.
Comparator circuits in integrated circuits such as, for example, a CMOS integrated circuit, are typically configured as a differential amplifier responsive to a difference in voltage between respective inputs to the amplifier. Input and output stages of such comparator circuits are coupled to a constant current source, usually employing current mirror circuits, for providing a constant current to both the common mode terminal of the amplifier and to the output stages. The output stages are coupled to be driven by outputs from the amplifier.
In a conventional CMOS comparator circuit, the differential amplifier uses one stage of the current mirror circuit as a load. The output signals from the differential amplifier drive a common source transistor stage. An inverter is coupled to the output transistor stage to buffer its output. Due to the topology of the conventional comparator circuit, its AC response is limited. The drain and gate capacitance of the current mirror transistors and the gate capacitance of the common source transistor stage slow the circuit response time. Further, since the input common mode voltage determines the output swing of the differential amplifier, the response time is also affected by input common mode voltage. Unsymmetrical drive of the common source stage and output inverter also creates a skew in high-to-low and low-to-high response times.